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E2U0010-28-81
Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999
Semiconductor Single Chip CODEC
This version: Aug. 1998 MSM6996H/6996V/6997H/6997V/6998/6999 Previous version: Nov. 1996
GENERAL DESCRIPTION
The MSM6996H/MSM6996V/MSM6997H/MSM6997V/MSM6998/MSM6999 are a single-channel CODEC CMOS ICs containing filters for A/D and D/A converting of the voice signal ranging from 300 Hz to 3400 Hz.
FEATURES
* Compliance with ITU-T companding Law MSM6996H/MSM6996V/MSM6998 : A-law MSM6997H/MSM6997V/MSM6999 : m-law * Capable of independent operation of transmission and reception * Transmission clock in the range of 64 kHz to 2048 kHz * Adjustable transmit gain * 600 W drive for analog output MSM6996H/MSM6996V/MSM6997H/MSM6997V single end drive MSM6998/MSM6999 Push-pull drive * Built-in analog loop back fanction MSM6996V/MSM6997V * Built-in reference voltage source * Low Power Dissipation (60 mW to 70 mW Typ.) * Package options : 16-pin plastic DIP (DIP16-P-300-2.54) (Product name : MSM6996HRS/MSM6997HRS) (Product name : MSM6996VRS/MSM6997VRS) (Product name : MSM6998RS/MSM6999RS) 16-pin cer DIP (DIP16-G-300-2.54-1) (Product name : MSM6996HAS/MSM6997HAS) (Product name : MSM6996VAS/MSM6997VAS) (Product name : MSM6998AS/MSM6999AS) 24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name : MSM6996HGS-K/MSM6997HGS-K) (Product name : MSM6996VGS-K/MSM6997VGS-K) (Product name : MSM6998GS-K/MSM6999GS-K)
1/21
Semiconductor
MSM6996H/6996V/6997H/6997V/6998/6999
BLOCK DIAGRAM
MSM6996H/V MSM6997H/V
AIN+ AIN- GSX VDD VSS AG DG *2 TMC
+ -
SAMPLE
Pre Filter 5th LPF 3rd HPF Auto Zero Voltage REF.
COMP
Transmit PLL
XSYNC
C Ladder
SAR
Transmit Controller
XCLOCK PCMOUT *1 PDN/BS PCMIN RCLOCK RSYNC
T.PWD R.PWD C Ladder
- +
Receive Controller Receive PLL
AOUT
5th LPF
*1 BS : Only MSM6997H/V *2 Only MSM6996V, MSM6997V
MSM6998, MSM6999
AIN+ AIN- GSX VDD VSS AG DG AOUT-
+ - + -
SAMPLE
5th LPF 3rd HPF Auto Zero
Pre Filter
COMP
Transmit PLL
XSYNC
Voltage REF.
C Ladder
SAR
Transmit Controller
XCLOCK PCMOUT *3 PDN/BS PCMIN RCLOCK RSYNC
T.PWD R.PWD R
5th LPF
C Ladder
R AOUT+
- +
Receive Controller Receive PLL
*3 BS : Only MSM6999
2/21
Semiconductor
MSM6996H/6996V/6997H/6997V/6998/6999
PIN CONFIGURATION (TOP VIEW)
AIN+ 1 AIN- 2 GSX 3 AG 4 AOUT 5 NC 6 VDD 7 PCMIN 8 16 VSS 15 PCMOUT 14 PDN/BS 13 DG 12 XSYNC 11 RSYNC 10 XCLOCK AIN+ 1 AIN- 2 GSX 3 AG 4 AOUT 5 TMC 6 VDD 7 16 VSS 15 PCMOUT 14 PDN/BS 13 DG 12 XSYNC 11 RSYNC 10 XCLOCK AIN+ 1 AIN- 2 GSX 3 AG 4 AOUT+ 5 AOUT- 6 VDD 7 16 VSS 15 PCMOUT 14 PDN/BS 13 DG 12 XSYNC 11 RSYNC 10 XCLOCK 9 RCLOCK
9 RCLOCK PCMIN 8
9 RCLOCK PCMIN 8
NC : No connect pin
16-Pin Plastic DIP MSM6996HRS MSM6997HRS
16-Pin Plastic DIP MSM6996VRS MSM6997VRS
16-Pin Plastic DIP MSM6998RS MSM6999RS
AIN+ 1 AIN- 2 GSX 3 AG 4 AOUT 5 NC 6 VDD 7 PCMIN 8
16 VSS 15 PCMOUT 14 PDN/BS 13 DG 12 XSYNC 11 RSYNC 10 XCLOCK
AIN+ 1 AIN- 2 GSX 3 AG 4 AOUT 5 TMC 6 VDD 7
16 VSS 15 PCMOUT 14 PDN/BS 13 DG 12 XSYNC 11 RSYNC 10 XCLOCK
AIN+ 1 AIN- 2 GSX 3 AG 4 AOUT+ 5 AOUT- 6 VDD 7
16 VSS 15 PCMOUT 14 PDN/BS 13 DG 12 XSYNC 11 RSYNC 10 XCLOCK 9 RCLOCK
9 RCLOCK PCMIN 8
9 RCLOCK PCMIN 8
NC : No connect pin
16-Pin Cer DIP MSM6996HAS MSM6997HAS
16-Pin Cer DIP MSM6996VAS MSM6997VAS
16-Pin Cer DIP MSM6998AS MSM6999AS
3/21
Semiconductor
MSM6996H/6996V/6997H/6997V/6998/6999
AIN+ 1 AIN- 2 GSX 3 AG 4 AG 5 NC 6 NC 7 AOUT 8 NC 9 NC 10 VDD 11 PCMIN 12
24 VSS 23 PCMOUT 22 PDN/BS 21 DG 20 NC 19 NC 18 NC 17 NC 16 XSYNC 15 RSYNC 14 XCLOCK 13 RCLOCK
AIN+ 1 AIN- 2 GSX 3 AG 4 AG 5 NC 6 NC 7 AOUT 8 NC 9 TMC 10 VDD 11 PCMIN 12
24 VSS 23 PCMOUT 22 PDN/BS 21 DG 20 NC 19 NC 18 NC 17 NC 16 XSYNC 15 RSYNC 14 XCLOCK 13 RCLOCK
NC : No connect pin
24-Pin Plastic SOP MSM6996HGS-K MSM6997HGS-K
NC : No connect pin
24-Pin Plastic SOP MSM6996VGS-K MSM6997VGS-K
AIN+ 1 AIN- 2 GSX 3 AG 4 AG 5 NC 6 NC 7 AOUT+ 8 NC 9 AOUT- 10 VDD 11 PCMIN 12
24 VSS 23 PCMOUT 22 PDN/BS 21 DG 20 NC 19 NC 18 NC 17 NC 16 XSYNC 15 RSYNC 14 XCLOCK 13 RCLOCK
NC : No connect pin
24-Pin Plastic SOP MSM6998GS-K MSM6999GS-K
4/21
Semiconductor
MSM6996H/6996V/6997H/6997V/6998/6999
PIN AND FUNCTIONAL DESCRIPTIONS
AIN+, AIN-, GSX These three pins are used for the transmit level adjustment. AIN+ is a non-inverting analog input pin which is connected to the non-inverting input of a transmit amplifier. AIN- is an inverting analog input pin which is connected to the inverting input of the transmit amplifier. GSX is a transmit amplifier output pin. Adjustment can be done by following method.
Analog Input
C1 R1 R2
AIN+
+
AIN- GSX
-
RC Active Filter
R3 AG
Gain = 1 +
R2 R3
< 10
Notes: 1. R2 + R3 > 10 kW 2. When the DC off-set voltage of analog input is more than 20 mV, C1 and R1 should provide for DC blocking. In this case, cut-off frequency of HPF, composed by R1 and C1, should be less than 30 Hz. 3. R1 should be less than 20 kW AG AG is an analog ground. AG is connected to the analog system ground. AOUT AOUT is the analog signal output pin for the MSM6996H/V and MSM6997H/V. The output voltage range is 5 VPP. This output can drive the 600 W resistor. AOUT+, AOUT- Analog output for the MSM6998 and MSM6999. The output signal amplitudes are 5 VPP. The AOUT- output is inverted to the AOUT+ output. These outputs can drive a 600 W impedance. VDD VDD is the positive power supply. The voltage supplied to this pin should be +5 V 5%. 5/21
Semiconductor PCMIN
MSM6996H/6996V/6997H/6997V/6998/6999
PCM signal input. The serial input PCM signal is converted from digital to analog, synchronizing with the synchronous signal RSYNC and clock signal RCLOCK. The data rate of PCM signal ranges from 64 kbps to 2048 kbps. The PCM signal is read at the falling edge of the clock signal and latched into the internal register when finished to read eight bits data. The top of the PCM data is specified by RSYNC pulse timing. RCLOCK Receive clock pulse input. The frequency of this clock pulse should be identified with the data rate of PCM input signal at the PCMIN pin. This RCLOCK signal can be a continuous clock or a burst clock with nine bits or more. In the case of a burst clock, input the following timing.
PCMIN
MSD 1 2
D2 3
D3 4
D4 5
D5 6
D6 7
D7 8
D8 9
RCLOCK RSYNC
9 Clocks are required
XCLOCK Transmit clock input. The PCM output data rate from the PCMOUT pin is set by this clock frequency. The applicable clock frequencies range from 64 kHz to 2048 kHz. This XCLOCK signal can be a continuous clock or a burst clock with nine bits or more. In the case of a burst clock, input the following timing.
PCMOUT
MSD 1 2
D2 3
D3 4
D4 5
D5 6
D6 7
D7 8
D8 9
XCLOCK XSYNC
9 Clocks are required
6/21
Semiconductor RSYNC
MSM6996H/6996V/6997H/6997V/6998/6999
Receive synchronizing signal input. Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive synchronizing signal. The whole timing signal in the receive section are synchronize by this synchronizing signal. This signal must be synchronize in phase with RCLOCK. The frequency should be 8 kHz 50 ppm to guarantee the AC characteristics of receive section. However, same as the RCLOCK frequency, this device can operate in the range of 8 kHz 2 kHz, with no guarantee of adherence to the electrical characteristics in this specification as a catalogue value. Fixing this signal to logic "1" or "0", the receive circuit is driver in a power down state. XSYNC Transmit synchronizing signal input. The PCM output signal from the PCMOUT pin is output in synchronization with this transmit synchronizing signal. All transmit timing signals are triggered to synchronize with this signal. This signal should be synchronized in phase with XCLOCK pulse. The frequency should be 8 kHz 50 ppm to guarantee the AC characteristics of transmit section. Fixing this signal to logic "1" or "0", the transmit circuit is driver in a power down state. DG Ground of digital signal. This pin is electrically separated from the AG pin in this device. The DG pin must be connected to the AG pin on the printed circuit board to make common to the AG pin. PDN/BS Power down signal input. When this input is held at low level more than 1 ms, the device is put into the power-down mode. PCMOUT PCM signal output. The PCM output signal is output in synchronization with the rising edge of XCLOCK pulse orderly from MSD first. (The first bit of the PCM signal may output at the rising edge of XSYNC pulse, according to the timing of XSYNC and XCLOCK pulse.). During the PCMOUT signal output except the 8-bit pulses, the pin is in an open state, therefore, multiple connections by wired-OR are easily possible at this pin. The code companding law and output code format depend on ITU-T Recommendation G.711, and for the MSM6996H, MSM6996V, and MSM6998 (A-law) the output PCM signals are obtained by inverting the even bits of signals.
Input/Output Level +Full scale +0 -0 -Full scale 1 1 0 0 0 1 1 0 PCMIN/PCMOUT MSM6996 (A-law) MSM6998 (A-law) 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 MSM6997 (m-law) MSM6999 (m-law) 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
7/21
Semiconductor TMC
MSM6996H/6996V/6997H/6997V/6998/6999
Control signal input for mode selection. This pin select the normal operating mode or analog loop-back mode.
TMC Input > 2.0 V < 0.8 V Mode Normal operation Analog loop-back
AIN
+ -
TRANSMIT BPF
AD
PCMOUT
AOUT
+ - AG
RECV LPF
DA
PCMIN
Signal flow in normal operating mode Signal flow in analog loop-back mode
VSS Negative voltage power supply. The range of power supply voltage is -5 V 5%.
8/21
Semiconductor
MSM6996H/6996V/6997H/6997V/6998/6999
ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Analog Input Voltage Digital Input Voltage Storage Temperature Symbol VDD VSS VAIN VDIN TSTG Condition -- -- -- -- -- Rating 0 to 7 -7 to 0 VDD -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -55 to +150 Unit V V V V C
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage Operating Temperature Analog Input Voltage Input High Voltage Input Low Voltage Clock Frequency Sync Pulse Frequency Clock Duty Ratio Digital Input Rise Time Digital Input Fall Time Transmit Sync Timing Receive Sync Timing Transmit Sync Pulse Width Receive Sync Pulse Width PCMIN Set-up Time PCMIN Hold Time BS Set-up Time * BS Hold Time * Analog Output Load Symbol VDD VSS Ta VAIN VIH VIL fC fS DL tIr tIf tXS tSX tRS tSR tWX tWR tDS tDH tBS tBH RAL CAL Digital Output Load Allowable Analog Input Offset Voltage RDL CDL VIO Condition -- -- -- Connect AIN- and GSX XSYNC, XCLOCK, PCMIN, RSYNC, RCLOCK, TMC, PDN/BS XCLOCK, RCLOCK XSYNC, RSYNC XCLOCK, RCLOCK XSYNC, XCLOCK, PCMIN, RSYNC, RCLOCK (Fig. 1) XCLOCKAEXSYNC (Fig. 2) XSYNCAEXCLOCK (Fig. 2) RCLOCKAERSYNC (Fig. 2) RSYNCAERCLOCK (Fig. 2) -- -- -- -- -- -- AOUT, AOUT+, AOUT- GSK -- -- Transmit gain stage, Gain = 1 Transmit gain stage, Gain = 10 Min. 4.75 -5.25 0 -- 2.0 0 64 -- 40 -- -- 50 100 50 100 1/fc 1/fc 100 100 200 200 600 10 -- 1 -- -200 -20 Typ. 5 -5 25 -- -- -- -- 8 50 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
(Ta = 0C to 70C) Max. 5.25 -4.75 70 5 VDD 0.8 2048 -- 60 50 50 -- -- -- -- -- -- -- -- -- -- -- -- 100 -- 100 +200 +20 Unit V V C VP-P V V kHz kHz % ns ns ns ns ns ns ms ms ns ns ns ns W kW pF kW pF mV
* : The value for the MSM6997 and MSM6999
9/21
Semiconductor
MSM6996H/6996V/6997H/6997V/6998/6999
ELECTRICAL CHARACTERISTICS
DC and Digital Interface Characteristics
(VDD = +5 V 5%, VSS = -5 V 5%, Ta = 0C to 70C) Parameter Power Supply Current (Operating) Power Supply Current (Stand-by) Input High Voltage Input Low Voltage Input Leakage Current Output Low Voltage Output Leakage Current Analog Output Offset Voltage Input Capacitance Analog Input Resistance Symbol IDD1 ISS1 IDD2 ISS2 VIH VIL IIH IIL VOL IOH VOFF CIN RIN -- fIN < 3.4 kHz -- Condition XCLOCK, RCLOCK 2048 kHz * * Min. -- -- -- -- 2.2 -- -- -- -- -- -150 -- -- Typ. 7.0 6.5 -- -- -- -- < 0.5 < 0.2 0.1 <5 0 5 1 Max. 12 14 12 14 3.0 1.5 -- 0.8 2.0 0.5 0.4 10 +150 -- -- mA V V mA V mA mV pF MW mA Unit
--
* : The upper is specified for the MSM6996/MSM6997 and the lower for the MSM6998/MSM6999
10/21
Semiconductor AC Characteristics
MSM6996H/6996V/6997H/6997V/6998/6999
(VDD = +5 V 5%, VSS = -5 V 5%, Ta = 0C to 70C) Condition Parameter Symbol LOSS T1 LOSS T2 Transmit Frequency Response LOSS T3 LOSS T4 LOSS T5 LOSS T6 LOSS R1 LOSS R2 Receive Frequency Response LOSS R3 LOSS R4 LOSS R5 SD T1 Transmit Signal to Noise Ratio *1 SD T2 SD T3 SD T4 SD T5 SD R1 Receive Signal to Noise Ratio *1 SD R2 SD R3 SD R4 SD R5 GT T1 GT T2 Transmit Gain Tracking GT T3 GT T4 GT T5 GT R1 GT R2 Receive Gain Tracking GT R3 GT R4 GT R5 1020 or 820 1020 or 820 1020 or 820 1020 or 820 Freq. (Hz) 60 300 820 2020 3000 3400 300 820 2020 3000 3400 3 0 -30 -40 -45 3 0 -30 -40 -45 3 -10 -40 -50 -55 3 -10 -40 -50 -55 -0.2 -0.4 -0.8 -0.2 -0.4 -0.8 -0.2 0 -0.1 -0.1 0 36 36 36 31 26 36 36 36 31 26 -0.2 0 Level (dBm0) 20 -0.15 -0.15 -0.15 0 -0.1 -- -- Reference -- -- -- -- Reference -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reference -- -- -- -- Reference -- -- -- +0.2 +0.4 +0.8 dB +0.2 +0.4 +0.8 +0.2 dB +0.2 +0.2 0.8 -- -- -- -- -- -- -- -- -- -- +0.2 dB dB dB +0.25 +0.25 0.8 +0.2 -- +0.25 dB Min. Typ. Max. Unit
Note: *1 The measurement is taken with P-message filter
11/21
Semiconductor AC Characteristics (Continued)
MSM6996H/6996V/6997H/6997V/6998/6999
(VDD = +5 V 5%, VSS = -5 V 5%, Ta = 0C to 70C) Condition Parameter Idle Channel Noise *1 Absolute Gain *2 Absolute Delay Time Transmit Receive Transmit Receive Symbol NIDL T NIDL R AV T tD tGD T1 tGD T2 Transmit Group Delay Time *3 tGD T3 tGD T4 tGD T5 tGD R1 tGD R2 Receive Group Delay Time *3 tGD R3 tGD R4 tGD R5 Crosstalk Attenuation Out-of-Band Spurious Intermodulation Distortion Discrimination VDD Noise Rejection Ratio VSS Noise Rejection Ratio Transmit Receive Transmit Receive T to R R to T CR T CR R S IMD 1 DIS PPSR T PPSR R 0 to 300 NPSR T NPSR R tSD Digital Output Delay Time tXD1 tXD2 tXD3 Digital Output Fall Time tDO RDL = 2 kW CDL = 100 pF kHz 200 mVp-p Freq. (Hz) -- --
1020 or 820
Level (dBm0) -- -- 0 0 0
Min. -- -- -0.5 -0.5 -- -- --
Typ. -- -- 0 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 30 30 30 30 150 100 100 180 20
Max. -75 -75 +0.5 +0.5 0.52 0.75 0.35 0.125 0.125 0.75 0.75 0.35 0.125 0.125 0.75 66 66 -30 -35 -- -- -- -- -- 300 300 300 300 100
Unit
dBmOp dB ms
AV R 1020 or 820 -- 500 600 1000 2600 2800 500 600 1000 2600 2800
1020 or 820 1020 or 820 300 to 3400
0
-- -- -- -- --
ms
0
-- -- -- -- -- -- -- 30 -- -- -- -- 50 50 50 50 --
ms
-- 0 -4 0
dB dBmO dBmO dB
fa = 470 fb = 320 4.6 kHz to 72 kHz
dB
ns
ns
Notes: *1 The measurement is taken with P-message filter *2 MSM6996/MSM6998 0 dB = 1.231 Vrms MSM6997/MSM6999 0 dB = 1.227 Vrms *3 Reference : 1800 Hz
12/21
Semiconductor
MSM6996H/6996V/6997H/6997V/6998/6999
TIMING DIAGRAM
Wave Time Measurement Level
2.4 V 1.4 V 0.4 V tIr tWX tWR
2.4 V 1.4 V 0.4 V tIf tDOf
Note: Timing between signal waves is judged at 1.4 V
Figure 1
Basic Timing
XCLOCK
1 tXS tSX
2
3 1/fC
4
5
6
7
8
9
10
, ,,
XSYNC tWX tXD1 tXD2 MSD tXD3 PCMOUT tSD D2 D3 D4 D5 D6 D7 D8 Note 1): When tXS 1/2 fc, the Delay of the MSD bit is defined as tXD1. When tSX 1/2 fc, the Delay of the MSD bit is defined as tSD. 1 2 3 4 5 6 7 RCLOCK 8 9 10 tRS tSR RSYNC tWR tDS tDH D3 PCMIN MSD D2 D4 D5 D6 D7 D8 Invalid Data Note 2): Note 3): Transmit synchronizing and clock pulse, and Receive synchronizing and clock pulse may be asynchronous mutually. The threshold level is 1.4 V.
Transmitter Section
Receiver Section
Figure 2
13/21
Semiconductor
MSM6996H/6996V/6997H/6997V/6998/6999
Timing for 7 bits Decode (Specified for MSM6997/6999)
,,,
RSYNC PCMIN
12 34 5678 12 34 5678 12 34 5678 12 34 5678 9 12 34 5678 9 12 34 5678 9
RCLOCK
BS
Decoder Operation
Timing for Bit-steal Function Setting
RSYNC
PCMIN
RCLK
PDN/BS
Notes: Follow these procedures when the Bit-steal function is used: 1. Set the RSYNC pin to OFF ("L") after the PDN/BS pin is set at "H" for 10ms or more. 2. Set the RSYNC to ON after a pulse is input at the PDN/BS pin. 3. The Bit-steal function starts to operate.
,,,
Allowable Range Disable tBS tBH 8 Bits Decode 7 Bits Decode
8 Bits Decode
Figure 3
~
125 ms
more than 10ms
~
~
more than 10ms
~
~
~
14/21
Semiconductor
MSM6996H/6996V/6997H/6997V/6998/6999
APPLICATION CIRCUIT
Basic Circuit
PCM OUT IN XTAL 2.048 MHz 10 M 2 kW +5 V OUT PDN/BS 4049 4049 CLOCK XR SYNC XR DG AG VSS VDD IN GSX AIN- AIN+ AOUT ANALOG IN OUT
14 Q4 REC 15 10 9
+5 V 16 6 Q4 M4520RS R 8 7 EC 21 Power Down 1 : NOR 0 : Power Down
+ -
- 10 mF + 10 mF
Note 1 0V -5 V +5 V
+5 V
DG
Notes: 1. Insert diode for preventing from Latch-Up at turn on Power. Recommended Diode Specification. * High Speed Switching * Allowerable Power dissipation 250 mW to 300 mW * Forward Voltage Drop < 1.3 V (at 100 mA) 2. AG and DG must be connected in the printed circuit board mounted this device, for preventing from Latch-Up.
15/21
Semiconductor
MSM6996H/6996V/6997H/6997V/6998/6999
Example of Multi-Channel Connections (8ch)
74161(1) 512 kHz +5 V 2 1 7 10 9 CK CLR EP ET LO QA QB QC QD CO 14 13 12 11 15 PCM XC OUT XS No.1 RC PCM RS IN No.4 No.5 No.6 No.7 +5 V 1 kW Multiple PCM
74161(2) +5 V 2 1 7 10 9 CK QA 14 CLR QB 13 EP ET LO
QA QB QC QD +5 V QE 9 CLR QF 1 QG A 2 B QH 74164
9 CK
3 4 5 6 10 11 12 13
No.2
No.3
No.8
Example of Multi-Channel Timing
74161(1) QC Output 74161(2) QB Output QA 74164 Output QB QC QH Multiple PCM
7 8 No.1
MSD
2
3
4
5
6
7
8
LSD
No.1
2
3
4
5
6
7
8
512K CLK
16/21
Semiconductor
MSM6996H/6996V/6997H/6997V/6998/6999
Transmit and Receive Level Adjustment (MSM6996H/V, MSM6997H/V)
a. Transformer of turns ratio 1 : 1 1:1 4WS 600 W 1:1 4WR 600 W 600 W AG 1 AIN+ 2 AIN- 3 GSX AOUT
R1 20 kW 600 W 5
600 W Attenuator b. Transformer of turns ratio 1 : 2 2:1 4WS 600 W 2:1 4WR 600 W 300 W AG 1 AIN+ 2 AIN- 3 GSX AOUT
When R1 is open and the attenuator is set at 0 dB, 4 WS maximum input level = +7.17 + LT (dBm) 4 WR maximum output level = +1.15 - LT (dBm) LT : Transformer loss
R1 20 kW 300 W 5
When R1 is open and the attenuator is set at 0 dB, 4 WS maximum input level = +10.18 + LT (dBm) 4 WR maximum output level = +4.16 - LT (dBm) LT : Transformer loss
300 W Attenuator
Transmit and Receive Level Adjustment (MSM6998, MSM6999)
1:1 4WS 600 W 1:1 4WR 600 W 600 W AG 1 AIN+ 2 AIN- 3 GSX AOUT+
R1 20 kW 300 W 5
300 W 6 AOUT- 600 W Attenuator
When R1 is open and the attenuator is set at 0 dB, 4 WS maximum input level = +7.17 + LT (dBm) 4 WR maximum output level = +7.17 - LT (dBm) LT : Transformer loss
17/21
Semiconductor
MSM6996H/6996V/6997H/6997V/6998/6999
RECOMMENDATIONS FOR ACTUAL DESIGN
* To assure proper electrical characteristics, use bypass capacitors with excellent high frequency characteristics for the power supply and keep them as close as possible to the device pins. * Connect the AG pin and the DG pin each other as close as possible. Connected to the system ground with low impedance. * Mount the device directly on the board when mounted on printed circuit board. Do not use IC sockets. If an IC socket is unavoidable, use the short lead type socket. * When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave source such as power supply transformers surround the device. * Keep the voltage on the VDD pin not lower than -0.3 V and the voltage on the VSS pin more than +0.3 V even instantaneously to avoid latch-up phenomenon when turning the power on. * Use a low noise (particularly, low level type of high frequency spike noise or pulse noise) power supply to avoid erroneous operation and the degradation of the characteristics of these devices.
18/21
Semiconductor
MSM6996H/6996V/6997H/6997V/6998/6999
PACKAGE DIMENSIONS
(Unit : mm)
DIP16-P-300-2.54
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.99 TYP.
19/21
Semiconductor
MSM6996H/6996V/6997H/6997V/6998/6999
(Unit : mm)
DIP16-G-300-2.54
16 9
1
8
7.50MAX
20.00MAX
7.62
1.000.10
1.500.10
4.100.40
5.10MAX
SEATING PLANE
0.51MIN
2.54MIN
+0.1 0.25-0 5 .05
15 0~
0.80TYP
2.54
0.500.10
0.25 M
20/21
Semiconductor
MSM6996H/6996V/6997H/6997V/6998/6999
(Unit : mm)
SOP24-P-430-1.27-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.58 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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